I.
The traditional definition of Moore’s Law is The density of transistors on a semiconductor chip doubles on average every 18-24 months.
It was first proposed in April 1965 by Gordon Moore, the founder of the chip company Intel, in a paper called «Cramming more components onto Integrated Circuit» (Cramming more components into Integrated Circuit)…
In August 2013, Bob Colwell, who once worked for Intel as the chief designer, declared at an industry conference in Chicago: Moore’s Law in the chip industry is about to end.
«From the time frame of the plan, I think that 2020 may be the earliest end of Moore’s Law. You may be able to convince me to drag it to 2022, but no matter it (gate length, minimum line width of the crystal gate) is 7 nanometers, Or 5 nanometers, this (the end of Moore’s Law) is a big deal.» (The diameter of an ordinary human hair is about 75,000 nanometers)
Colwell, not the first, nor the last, predicted the end of Moore’s Law.
Moore himself predicted in 1995 that Moore’s Law would end in 2005.
In 2015, Moore himself once again predicted that Moore’s Law will end in 2025.
The most recent various predictions about the end of Moore’s Law, the main reason is that by 2025 if the gate length is reduced to only 3 nanometers, its length is only equivalent to the size of ten atoms. At this scale, the way electrons behave will enter the field of the uncertainty principle of quantum mechanics, and the reliability of transistors will be completely impossible to guarantee. In addition, at this scale, the heat dissipation of transistors and the production cost control of chips seem to be insurmountable technical challenges.
Will Moore’s Law really end?
If so, does it mean that the development of science and technology will be stagnant, and humans will eat together on the earth and wait for death?
If not, what does it mean for the progress of human civilization in the future?
II.
Before looking to the future, it is very necessary to review the evolution of Moore’s Law over the past fifty years.
The concept of transistor density originally proposed by Moore in the 1965 paper is not the maximum number of transistors that can be placed on the chip, but the optimal value of the number of transistors from the perspective of production cost.
When producing chips, increasing the number of transistors generally reduces the unit cost of transistors. However, when the number exceeds a critical point, the probability of chip production defects increases and begins to offset the benefits of increased density. In the design and production of integrated circuits, it is ultimately necessary to seek one The best point.
Moore predicted in 1965 that the density of transistors would double every year within ten years. By 1975, the number of transistors on a chip would increase from 64 in 1965 to 65,000 in 1975.
Later, a memory chip produced by Intel in 1975 (with an area of a quarter square inch, equivalent to 161 square millimetres) reached 32,000 transistors, which was very close to Moore’s initial prediction.
In 1975, Moore summarized the main reasons for the increase in chip density in the previous ten years in a paper:
1. Miniaturization of transistors
2. Increased chip area
3. New design techniques improve space utilization
However, the improvement in space utilization is ultimately limited, so Moore revised his forecast in 1975 to change the growth rate of transistor density from doubling every year to doubling every two years.
Take memory chips as an example. In 2000, DRAM had 256,000,000 transistors on an area of 204 square millimetres. Compared with 1975, the density of transistors has increased by 6,300 times in 25 years. (If it is doubled in two years according to Moore’s Law Speed, 25 years is about 5800 times increase, basically relatively close)
The storage capacity of the corresponding chip has increased from 0.001 Mb to 256 Mb, an increase of 250,000 times.
In traditional engineering design, it is often necessary to weigh the pros and cons of multiple factors. But for a long time, the miniaturization of transistors has not only increased the density in practice but also made the transistor faster and lower energy consumption. There is no need to worry about other factors. limit.
On average, the generation of chip production technology is changed every two years, the gate length is reduced by 30% (x 0.7), the corresponding transistor density is doubled, the delay between transistors is reduced by 30%, the corresponding clock frequency is increased by 40%, and the voltage of the transistor is reduced by 30 %, the unit energy consumption is reduced by 50%. Since the overall number of transistors doubles, the overall energy consumption remains the same, but the overall circuit is 40% faster.
However, at the beginning of this century, the miniaturization of transistors encountered a bottleneck. When the gate length was less than 100 nanometers, the problem of transistor leakage became serious and became a problem that cannot be ignored.
III.
The essence of the transistor is to use the «on» and «off» states to represent the 1 and 0 in the binary system.
The so-called Field-Effect Transistor in integrated circuits is mainly composed of three parts: Source, Gate, and Drain. The gate is essentially a capacitor, which is applied to it When voltage is applied, the channel under the gate connects the source and drain, and the transistor is turned on, which represents the state of «1». When the voltage is cancelled, the current drops to zero and the transistor is turned off, which represents the state of «0».
People usually say that the clock frequency of the CPU is the speed of the transistor switching. 1 GHz means that it can switch one billion times in 1 second.
Why did the human computing revolution choose transistors?
Because of the continuous miniaturization of transistors, the computing power per unit production cost has continued to increase exponentially.
In contrast, the ancient abacus, the speed of the abacus fiddle (similar to the speed of a transistor switch), and the capacity of data have not been substantially improved for more than two thousand years.
IV.
With the continuous miniaturization of transistors, various leakage problems have become a major obstacle to the development of Moore’s Law. Leakage means a great increase in energy consumption, and the chip overheats or even fails.
A typical type of leakage is the so-called «Gate Oxide Leakage».
Under the gate of the traditional field-effect transistor is a layer of silicon oxide (Silicon Oxide) material, and its thickness decreases with the miniaturization of the transistor (otherwise it will affect the capacitance of the gate and the performance of the transistor). When the gate length is reduced to the order of 45 nanometers, the effective thickness of silicon dioxide is only about one nanometer. Due to the effect of quantum tunnelling, it will cause serious leakage of the gate.
In the end, Intel’s solution after tens of thousands of experiments is to use a «high dielectric» material, which is based on metal hafnium oxide, instead of silicon dioxide. The physical Vthickness is not reduced, but it does not affect the capacitance of the gate.
The 45-nanometer chip introduced by Intel in 2007 has reduced gate leakage by more than 90% compared to the previous generation technology.
V.
Another type of leakage comes from the so-called «Short Channel Effect» (Short Channel Effect) problem. In short, the gate length of the transistor keeps shrinking, the threshold voltage of the transistor’s conduction keeps dropping, and there is still a weak voltage at zero voltage. Electric current passes.
The essence of this problem is that when the gate is short, the drain itself becomes a capacitor and competes with the gate. The smaller the gate, the farther away from the gate, between the source and the drain The leakage current cannot be controlled. As shown in the figure below.
In 1996, when the industry was still producing 250nm chips, the public view was that it was almost impossible to miniaturize transistors below 100nm. But the Defense Advanced Research Projects Agency (DARPA) was already thinking about miniaturization to 25nm. , The leakage caused by the short channel effect is a challenge.
Professor Hu Chengming of the University of California, Berkeley, received DARPA funding in 1997 and proposed the FinFET design concept. The essence of the idea is to wrap the transistor on the three sides with a gate so that any channel between the source and the drain is separated from The gate is not too far away, and the leakage is caused by the short channel effect is greatly reduced.
This design, because it is shaped like a fin (Fin), is also called FinFET. (FET is the abbreviation of «Field Effect Transistor»)
More than ten years later, after overcoming various production technology challenges, Intel used FinFET technology for the first time in 22nm chips in 2011. This technology was called by Gordon Moore «the most radical in the semiconductor industry in the past 40 years.» Changes».
VI.
If history is a lesson, breaking the physical limits of transistor miniaturization is not as pessimistic as observers are now. A problem that seemed insurmountable at first would have unexpected solutions from a different perspective.
Moore’s Law originally talked about the density of transistors.
Increased density means miniaturization of transistors, which means:
- The unit cost of integrated circuits,
- In the case of constant energy consumption,
- Its computing power will continue to improve.
Miniaturization is just the appearance. In the case of the same production cost and energy consumption, improving computing power is the essence of Moore’s Law. According to this idea, there are actually many ways to promote Moore’s Law.
VII.
Before 2002, with the increase in chip density, the clock frequency of the CPU has also been increasing. For ordinary consumers, the frequency of the CPU represents the speed of the computer. The first IBM PC shipped in 1981, the frequency of the CPU was 4.77 Megahertz, which is equivalent to 4.77 million clock cycles per second. Assuming that the CPU can run instruction in one clock cycle, the higher the frequency, the faster it will be.
In 1995, the clock frequency of the Pentium chip reached 100 MHz, which is more than twenty times that of 1980.
In 2002, the clock frequency of Intel’s new Pentium chip exceeded 3000 MHz (3 GHz) for the first time.
The first major physical constraint that limits the clock frequency is the hysteresis of the signal transmission between transistors. This is why the greater the transistor density, the higher the clock frequency can be.
After 2002, the increase in CPU clock frequency encountered a second technical bottleneck: energy consumption.
Simply put, the energy consumption of the CPU is approximately proportional to the third power of the clock frequency. After 3 GHz, the continued increase in the frequency will cause the chip to overheat and face the risk of burning.
In fact, after 2002, the clock frequency of Intel CPUs has mostly been between 2 GHz-4 GHz, and there has been no substantial increase in 14 years.
But the clock frequency no longer increases, it does not mean that CPU performance is stagnant. Just like the human brain, there has been no essential change in the past 200,000 years, but it does not mean that human civilization will not undergo ground-breaking progress.
At this time, the most useful idea is to find new dimensions to attack and solve problems.
VIII.
If the clock speed of the CPU is like the calculation speed of the human brain, then the memory read speed of the CPU is like the speed at which people can obtain information. This is the first different dimension of improving CPU performance.
People who have basic work or research experience will have this experience:
Most of the time, the bottleneck that limits work efficiency is: check information and find things.
If you can’t find it, you can only do it in a hurry.
Twenty years ago, researchers who searched for materials had to go to the library, and small libraries had to go to larger libraries if they had no materials. Before searching by computers, they needed to flip through the cards one by one. The time to find materials was just a few. Hours or more, surpassing the time for real research and analysis. This is completely different from today, where you can accurately search and download most of the world’s papers on the Internet within ten seconds.
The computer’s memory architecture is actually subdivided into Register (register), Cache (cache), Memory (memory), Disk (hard disk). And the cache can be subdivided into Level 1 Cache, Level 2 Cache, three-level cache, or even four-level cache.
For example, the data in the register is like the information written on the piece of paper in your hand. The amount of information is very small, but it is desirable to wait.
The first level cache, like a book on the desktop, has more information and can be obtained by reaching out;
The secondary cache, like a book in a drawer, can still be obtained soon after opening the drawer;
Memory, like a book on a shelf, stand up to find it;
The hard disk is the library’s materials, and it takes a few hours to go outside to find it.
Researchers, if they can’t get the materials they need quickly, have to run to the library every day, even if Newton/Einstein is reborn, the smart brain can only be like a high-speed CPU, idling ineffectively, and painfully coming and going to the library. Waiting on the road.
Take Intel’s i7-4770 CPU as an example, its clock frequency is 3.4 GHz. For the primary and secondary caches, the latency of reading data is generally 5-12 clock cycles, which is equivalent to about 2-4 nanoseconds. If you want to access the memory When reading data, the lag is about 70 nanoseconds, which is equivalent to more than 200 clock cycles. If the memory cannot be found, unfortunately, you have to search on the hard disk. The delay is more than 4 milliseconds (equivalent to 4 million nanoseconds), and then faster The CPU clock frequency of the CPU is also dead at this time.
IX.
With the development of Moore’s Law, the CPU clock speed is different from the read latency of ordinary memory (DRAM). The gap is increasing at a rate of 50% every year.
In order to alleviate this contradiction, the cache (Cache) first appeared on Intel’s 386 processor in 1985 in an external form.
The built-in cache on the real chip first appeared on the 486 processor in 1989, when the capacity was only 8 KB, and the capacity was increased to 16 KB in the 1990s.
If the cache capacity is too large, it will affect the search speed, so there are secondary and tertiary caches. There are many subtle design details, which are not shown here.
The cache is essentially a memory based on SRAM (Static Random Access Memory). SRAM is essentially a logic unit composed of six transistors, as shown in the figure below.
With the miniaturization of transistors, chip designers continue to add more built-in caches to the CPU chip.
Take the 14-nanometer i7-6560U processor produced by Intel in September 2015 as an example. It has two cores, each core has 64 KB of L1 cache, 256 KB of L2 cache, and shares a 4 MB The third-level cache.
The ratio of transistors used for cache to the transistors on the entire CPU chip has also changed from about 40% in the 486 eras to nearly 90% on many CPUs today. (Data source comes from a paper by Doug Burger, University of Wisconsin, «System-level Implications of Processor Memory Integration«)
In other words, the management of computing, nearly 90% of the connotation, is actually the management of memory.
No matter what industry you are in, if you can efficiently search and store massive amounts of data, you may have succeeded 90%.
X.
Another dimension to solve the CPU clock bottleneck problem is to increase the parallelism of the system and do more things at the same time.
Traditionally, a CPU chip has only one processor (core, also known as core or core). When the clock speed of a single CPU is difficult to increase, another idea of the chip designer is to add new ones on the same chip. The kernel allows multiple cores to process some calculations in parallel at the same time.
The first benefit of a multi-core CPU is energy saving. As mentioned earlier, the energy consumption of the processor is approximately proportional to the third power of the clock frequency. In theory, if the clock frequency of a core is reduced by half (the computing speed is also reduced by half), The energy consumption is only one-eighth of the original.
If the computing task to be solved can be easily divided into two parts and processed in parallel, then a dual-core CPU can reduce the overall power consumption to one-eighth of the original by reducing the core clock frequency while maintaining the same computing power. one.
Of course, this is only the theoretical best situation, and the factors affecting actual power consumption are much more complicated than this.
XI.
But – many application problems have various bottlenecks in their operation, and they cannot make full use of parallel computing, especially applications on ordinary personal computers. An example that opponents often quote is «a woman can have a child in nine months, but You can’t let nine women give birth to one child a month.”
After all the «buts», there is often another «but». If the goal is to give birth to one child in one month, this problem cannot be accelerated by parallelization. But – if the goal is to have as many as possible in nine months The child of, this problem can be achieved through the parallelization of nine women!
From a new perspective, changing the originally set goals will find a place for the existing technical methods. This principle requires special attention when designing parallel computing systems and thinking about solving other problems.
If it is said that ordinary personal computers should pay attention to the problem of giving birth to one child. Then, what supercomputers have to solve is the problem of giving birth to the largest number of children in nine months.
Take the world’s top supercomputer as an example. In 2000, the world’s number one supercomputer was IBM’s, ASCI White. It contains 8,000 cores, costs 100 million U.S. dollars, consumes three megawatts of power, and has a calculation speed of 7.2 TFLOPS. (Trillions of floating-point calculations per second, 64-bit floating-point calculations, the same below)
As of 2016, the world’s number one supercomputer is Wuxi’s Sunway Taihu Light. It contains 10 million cores, costs close to 300 million U.S. dollars, consumes 15 megawatts of power, and has a computing speed of 93,000 TFLOPS, which is ASCI. About 13,000 times that of White.
ASCI White’s processor core at the time had a clock frequency of only 375 Mhz. The core of Taihu Light had a clock frequency of about 1.45 GHz. Compared with that, the frequency of the core has increased by about four times in sixteen years.
However, the degree of parallelism measured by the number of cores has increased by a thousand or two hundred times.
This is also the main driving force for the progress of supercomputers and computing power in the past ten years.
XII.
Why can a new generation of supercomputers support such a large-scale parallel computing power? It was not possible before?
This is due to the data transmission rate of a new generation of network switches, which allows different cores and system nodes to communicate quickly and transmit massive amounts of data.
The company that provides switch chips to Sunway is Mellanox, headquartered in Silicon Valley and Israel. The bisected network bandwidth of the Sunway system is as high as 70 TB/sec, which is several million times the bandwidth of ordinary household broadband Internet access.
The improvement of the data transmission rate of the switch is also due to the continuous miniaturization of the transistor under Moore’s Law.
XIII.
People who are not familiar with the semiconductor chip production process often ask this question:
Why does the density of the chip only double in two years? Why can’t it be faster, quadruple, triple in two years? Why can’t we jump from 100 nanometers to 10 nanometers? It will take more than ten years to complete this process?
The simple answer to this question is: If a person has to eat seven steamed buns to be full, why can’t he just eat the seventh steamed bun first?
From another perspective, Moore’s Law is actually an economic issue of production costs.
It’s all for money.
The increase in chip density essentially reduces the production cost and power consumption of a single transistor, making the end product more competitive in the market.
Only the interests of the ultimate market will drive manufacturers to invest a lot of money into new production technologies.
How big is this funding scale?
In 1980, the cost of an ordinary fab was about 100 million U.S. dollars.
TSMC’s semiconductor wafer fab, Fab 15, which started construction in 2010, has a total cost of approximately 9.5 billion U.S. dollars.
Some experts estimate that by 2020, the cost of building the newest fab will increase to more than 15 billion U.S. dollars.
Why is the establishment of a chip production plant so expensive?
The production process of chips has become more and more complicated with the upgrading of technology. The production process includes thousands of steps and consumes a lot of water and electricity. Large-scale fabs generally cover an area of at least 100,000 square meters and use nearly 20,000 tons of water a day. Power consumption exceeds thirty megawatts.
XIV.
The most expensive part of the production process is something called the «learning curve».
Each machine in the plant may have hundreds of control knobs, and each knob needs to be set to the correct position. The most critical small part of the set requires continuous and long manual trials, feedback, and optimization. This requires a highly professionally trained team of scientists and engineers to work hard and debug for a long time to complete.
The production of fabs needs to have a sufficient capacity scale to debug. Debugging takes time, and time is money.
There is a concept called Yield for chips produced in fabs, which is the ratio of qualified chips to the total number of chips on a wafer. The process of production debugging is the process of improving the yield. The higher the yield, the unit lowers the cost of the chip.
The relationship between the unit cost of the final chip and the cumulative output of the chip is the so-called «learning curve». As shown in the figure below.
The learning curve is usually expressed by this mathematical formula:
Y = a X^b
Here Y is the average production cost of the cumulative unit product, a is the production cost of the first batch of products, X is the total number of products produced, and b is a negative number. The larger the absolute value, the faster the progress of the learning curve.
As a concept in industrial production, the «learning curve» was first proposed by Boeing engineer T. P. Wright in the 1930s. He found that the cost of aircraft manufacturing continued to decline as the number of production increased.
For example, the cost of the first new aircraft is 100 million U.S. dollars, the second may drop to 80 million, and the fourth to 64 million. The manufacturing cost of a single aircraft decreases with each doubling of the cumulative production quantity. 20%.
Why does the production cost continue to drop? The reasons include 1. Standardization of production processes and parts. 2. Increased worker efficiency. 3. Reduced errors. 4. Reduced material waste, etc.
This law is also reflected in the production of many other traditional manufacturing industries.
In the game of semiconductor production, the winner belongs to the manufacturer with the largest cumulative production scale, because the «learning curve» determines:
The lowest cost comes from the largest cumulative production scale.
XV.
From the decline curve of wafer production costs in a fab to the progress curve of Moore’s Law in the past 50 years, it can actually be seen as a natural manifestation of the «learning curve» law in the chip industry.
The main driving force supporting the progress of the «learning curve» and Moore’s Law is the ever-increasing massive demand for chips.
A larger memory chip stores files/photos/videos/songs, a faster chip transfers more data, and a smaller energy consumption chip increases the battery’s standby time.
These needs, and the real purchasing power behind them, can promote more funds to invest in the research and development of the semiconductor industry.
Worldwide semiconductor chip sales have grown from 55 billion U.S. dollars in 1990 to more than 300 billion U.S. dollars in 2015.
The cost of building a fab has ranged from 100 million U.S. dollars in the early 1980s to 1 billion U.S. dollars in the mid-1990s to an estimated 15 billion U.S. dollars in 2020. The size of the chip market can support the corresponding scale. Fab.
The decline in the production cost/price of a single transistor caused by the «learning curve» has spawned more new applications and demands, further expanded the semiconductor market, attracted more funds to invest in research and development, and formed a virtuous circle.
However, the completion of these advances requires eating steamed buns one by one in the existing semiconductor industry ecosystem. It is not in accordance with objective laws to expect another way to eat the seventh steamed bun and be full.
From an economic perspective, as long as this virtuous circle continues to operate undisturbed, there will naturally be a large amount of continuous investment of funds, and the various challenges encountered by Moore’s Law in engineering will eventually be overcome.
XVI.
In July 2012, a major event occurred in the semiconductor manufacturing industry: three-chip production giants, Intel/TSMC/Samsung, collectively a giant in the semiconductor lithography industry, the Dutch company ASML (ASML), promised to pay a total of 1.3 billion The euro’s research and development costs help it bear some of the risks of new technology development.
The three companies also purchased approximately 23% of ASML’s shares at a price of nearly 40 euros per share. (Four years later, in July 2016, ASML’s stock price was around 96 euros.)
The funds obtained by ASML are mainly used to accelerate the development of 450mm wafer-related equipment and the next generation of extreme ultraviolet lithography (EUV).
The lithography process accounts for nearly half of the cost of chip production. In order to ensure the technological development of the semiconductor industry chain and continue to advance in accordance with the roadmap of Moore’s Law, the chip giants went shirtless and directly injected huge amounts of money to accelerate the research and development of equipment manufacturers. This is the first time.
This also responds to an old Chinese saying: Money can make ghosts push more.
As long as there is a demand in the ultimate market, as long as there is a steady flow of capital injection, all engineering challenges can be overcome in the end.
XVII.
How much money will the future development of the semiconductor industry attract to push Morales (Rel’s Law)?
A 2015 report by consulting firm PricewaterhouseCoopers predicted that the output value of the global semiconductor industry would increase from US$330 billion in 2014 to US$430 billion in 2019. But their model at the time was mainly Suppose the demand for semiconductors in industrial production, automobiles/trolleys and the Internet of Things grows, without considering the explosion of artificial intelligence applications.
What does the further development of Moore’s Law mean for artificial intelligence?
It is mentioned that Nvidia’s DGX-1 supercomputing system requires only two hours to train Alexie’sneural network model with 60 million free parameters.
Roughly estimated, for the training of a neural network model containing 10 billion free parameters, DGX-1 will take more than three hundred hours, which is nearly two weeks. According to the estimation of the Danish scholar Bente Pakkenberg’s 2003 paper, The human cortex is equivalent to a neural network with 150 trillion free parameters. To simulate a model with the same complexity as the human brain, the computing power required is about 15,000 times that of DGX-1.
The IBM-led team is developing the next generation of supercomputer Summit, which is expected to be available in early 2018. This supercomputer system is expected to have a calculation speed of 200,000 FLOPS, which is equivalent to 5,000 times the 43 FLOPS speed of the DGX-1 system.
This computing ability should be able to partially simulate a neural network system as complex as the human brain, and through active self-learning to obtain the same complex abstract thinking ability as the human brain, rather than just simple listening, speaking, reading and writing.
The cost of the IBM Summit is about 320 million U.S. dollars. Assuming that its service life is as long as ten years, the calculated cost per hour is as high as three thousand U.S. dollars. Considering that the system consumes about 15 MWh, assuming that the electricity cost per kilowatt-hour is 5 U.S. cents, an hour of electricity costs $750.
The cost is close to four thousand dollars an hour, which sounds very expensive. But if you compare this number horizontally:
- Former U.S. President Clinton’s one-hour speech fee: $250,000
- Clinton’s daughter Chelsea Clinton, one-hour lecture fee at the University of Missouri: $65,000
- The average salary of CEOs of the top 500 listed companies in the United States is 13 million U.S. dollars a year.
- For ordinary engineers in Silicon Valley, assuming a basic salary of 200,000 U.S. dollars, plus various health insurance and stock benefits, the cost to the employer is about 300,000 U.S. dollars, which is equivalent to about 150 U.S. dollars per hour.
The competition faced by these successful people will be one:
A tireless workaholic who can study and work 24 hours a day / go to the toilet without eating or drinking tea.
Knowing astronomy on the top / knowing geography on the bottom / multilingual/rigorous thinking / rapid response / highly rational/wise man who meets people, talks to people, hells and talks to ghosts.
Exemplary employees who will not strike/ask for leave / change jobs / internal friction / sell their leaders, and consciously cut their salary by 30% every year according to Moore’s Law.
Amazon founder Bezos once said, «Your margin is my opportunity» (Your margin is my opportunity). As long as there are people in the world who earn high profits by selling their intelligence, there will be funds to promote artificial intelligence and The research and development of the chip technology behind it competes head-on with it.
XVIII.
Taking history as a lesson, it is precise because of a large amount of financial support that Intel found a «high dielectric constant» material to solve the problem of gate leakage during the production of 45-nanometer chips.
Also because of a large amount of capital investment, FinFET technology is implemented in 22nm chip production, which greatly alleviates the leakage problem under the short channel effect.
When the gate length is reduced to 5 nanometers after 2020, one possibility is that an engineering solution that no one has thought of at present will skip the limit of the uncertainty principle.
Another possibility is that when one dimension reaches its limit, improve product performance from another dimension to achieve equivalent results.
When the CPU clock frequency comes to an end, it is hard to work on the design of the memory architecture.
The speed of a single computing task cannot be improved, so the parallelism of the system is increased by increasing the bandwidth of the network switch and memory transmission.
The optimization of the hardware architecture reaches the extreme, and it is hard to work on the software design.
The plane is too crowded, so it turns to three dimensions.
XIX.
From a longer-term historical perspective, according to futurist Ray Kurzweil, Moore’s Law is only a few hundred years old, human computing technology, from the abacus to the hand-cranked mechanical computer, to the relay, to the vacuum tube, the transistor, and then to the big The evolution of scale integrated circuits has been a natural manifestation of the past fifty years.
In the development of computing technology, the law of economics has naturally selected large-scale integrated circuits that stand out. However, if silicon-based integrated circuits reach the limit of computing power at some point in the future, the same economic law will naturally be selected. The most economical technical solution that emerged at that time.
What will this future plan be? Will it be an integrated circuit made of gallium arsenide? Will it be a quantum computer? Or a new computing architecture based on DNA molecules? How far can Moore’s Law go?
It is unpredictable now. But if you believe that computing and communication capabilities will play an increasingly important role in the development of human economy and civilization, then more funds will continue to promote the research and development of computing technology, then Moore’s Law will continue in the future Go very far, very far.
The full text is over.